SmartNIC with SDN Offload
Virtual networking can consume a large share of a cloud host's CPU. Moving the SDN datapath into a programmable SmartNIC frees those cores and cuts latency — and an FPGA makes it practical to prototype.
Background & motivation
In a virtualized cloud, every packet to and from a VM traverses a software stack — an overlay network, security groups, load balancing, and a virtual switch such as Open vSwitch (OVS). At line rates of 100 GbE and beyond, that work burns host CPU cores that operators would rather sell as tenant compute, and it adds latency and jitter.
The answer, proven at hyperscale, is to offload that datapath to a SmartNIC / DPU. Microsoft Azure's Accelerated Networking (AccelNet) made FPGA-based SmartNICs the default virtual-NIC hardware across a fleet of more than a million hosts beginning around 2015, delivering host-offloaded networking at line rate.
Architecture: a programmable datapath
A SmartNIC pairs a programmable data plane — an FPGA or ASIC packet pipeline handling L2/L3 forwarding — with general-purpose cores that run the control plane and higher-layer functions. The classic SDN-offload pattern keeps the OVS control plane in software while pushing flow rules into a hardware switch on the NIC:
- OVS offload — flow rules are programmed into a hardware eSwitch (for example via vDPA / ASAP²), so the OVS datapath runs in hardware at line rate with little host CPU, using standard libraries like DPDK.
- VirtIO acceleration — the NIC presents a standard
virtio-netdevice to the guest while the datapath is accelerated in hardware, so no custom guest drivers are required. - P4-style pipeline — a parser → match-action → deparser pipeline describes packet processing; on an FPGA the match-action tables are reconfigurable, so new rules and protocols can be installed at runtime without recompiling the hardware.
Research prototypes that offload OVS to a P4-programmable FPGA SmartNIC have sustained line rate while cutting end-to-end packet-processing delay, confirming that the FPGA route is a credible path from idea to working silicon-class datapath.
How Ivy Microsystems helps
Build a SmartNIC on FPGA with a programmable packet pipeline that accelerates Open vSwitch and VirtIO, enabling flexible in-network processing at cloud scale. Our tools and IPs give you a starting point on your own FPGA platform:
- SoC Pilot — design the NIC SoC and datapath architecture on a canvas, integrate IP, and generate RTL with design-rule checking.
- Silicon IP — Networks-on-Chip for on-chip transport, DMA controllers for host and descriptor movement, and RISC-V cores for the control plane.
- Firmware Pilot — a low-code IDE with interactive emulation to bring up the OVS-offload agent and VirtIO path and validate the datapath against the SoC model before committing to hardware.